1. Field of the Invention
The invention relates in general to the fabrication of a metal via of multi-level interconnection in the process of forming a metal-oxide-semiconductor device (MOS), and more particularly to the method of forming an unlanded via of multi-level interconnection, making use of damascene scheme.
2. Description of the Related Art
The increasing of the integrality of the integrated circuited (IC) causes the insufficiency of the chip surface for formation of interconnection. To satisfy the requirement of more wiring lines as the device size is shrinking, a design of multi-level interconnection is needed for IC fabrication.
Conventionally, a via with wider line width, called a landed via, is frequently utilized to prevent misalignment and to ensure the tight contact of the metal via and metal wiring line. However, the landed via occupies extra chip surface area, which is not suitable for current IC fabrication process.
Therefore, as higher integrality is strongly required, an unlanded via, having equal line with as the wiring line, is developed. The chip surface area is less occupied by using the unlanded via so that the IC integrality can be increased. However, another problem arises by utilizing unlanded via, which is, the unlanded via can not completely fall on the metal wiring lines.
A process flow showing the formation of a conventional unlanded via of multi-level interconnection is illustrated through FIG. 1A to FIG. 1D. Referring first to FIG. 1A, a first metal layer 12, such as aluminum, is formed over a substrate 10, having a MOS device formed thereon. The first metal layer 12 is then patterned to form a first metal wiring line 12a, as shown in FIG. 1B. An inter-metal dielectric layer 14, such as silicon dioxide, is formed over the first metal wiring line 12a. The inter-metal dielectric layer 14 is next processed through chemical mechanical polish to planarize its surface.
Next, referring to FIG. 1C, the inner dielectric layer 14 is patterned to form a metal via 16, exposing the first metal wiring line 12a. A metal plug 18, such as a tungsten plug, is then formed in the metal via 16.
Referring to FIG. 1D, a second metal layer 19, such as aluminum, is formed over the inter-metal dielectric layer 14 and the metal plug 18. The second metal layer 19 is then patterned to form a second metal wiring line 19a, which are coupled to the metal plugs 18. A conventional unlanded via is therefore completed.
In the conventional processes of fabricating an unlanded via, misalignment tends to occur as the inter-metal dielectric layer 14 is patterned. The misalignment usually causes overetching, or more seriously, piercing of the inner dielectric layer 14 during the formation of the via. As the inter-metal dielectric layer 14 is pierced, the latter-formed metal plug 22 contacts with the devices formed therebeneath, which causes short circuit. The possible undesired metal vias are as shown in FIG. 2A and FIG. 2B. Referring to FIG. 2A, due to the misalignment and overetching during the formation of the via, the metal plug 22 penetrates the inter-metal dielectric layer 21, which therefore results in short circuit. Referring to FIG. 2B, even the metal plug 24 does not penetrate the inter-metal dielectric layer, a gap 26 is formed due to misalignment. The gap 26 causes difficulty in metal filling.
Forming an etching stop layer over the first metal wiring line has been proposed to dissolve the above-mentioned problem. However, forming an etching stop layer over a already formed first metal wiring line is a task.